1. Field of the Invention
The invention relates in general to a flat display, and more particularly to a flat display and a timing controller thereof for eliminating a shutdown residual image of the flat display by way of timing control.
2. Description of the Related Art
A flat display, such as a liquid crystal display (LCD), has the advantages of the high image quality, the small size, the light weight, the low driving voltage and the low power consumption. So, the flat display has been widely applied to consumer communication or electronic products, such as personal digital assistants (PDAs), mobile telephones, video recorder/players, notebook computers, desktop displays, mobile displays and projection television, and gradually replaces the cathode ray tube (CRT) to become the mainstream of the display.
In the typical architecture of the LCD, a residual image is frequently seen on the LCD panel after the LCD is shut down, or even cannot disappear after several seconds have elapsed. This phenomenon cannot satisfy the visual exception of the user and decreases the display quality of the LCD panel after a long period of time has elapsed. Taking a thin film transistor (TFT) LCD as an example, one of the main reasons for causing the shutdown residual image is that the discharge speed of the pixel electrode in the TFT LCD is too slow so that the charges cannot be quickly released and are remained in the liquid crystal capacitor after shutdown. Thus, the charges cannot be completely discharged after a period of time has elapsed.
FIG. 1 (Prior Art) is a schematic illustration showing a conventional LCD 10. As shown in FIG. 1, a timing controller (not shown in FIG. 1) outputs data to a pixel array 16 in the LCD 10. The pixel array 16 receives and writes scan rows of data using a source driver, and selects the scan rows of the to-be-written data by using a gate driver 12 so that an output frame is displayed on the LCD panel. In order to eliminate the phenomenon of the shutdown residual image when the LCD is shut down, a reset circuit 14 detects the variation of an operating voltage VDD to output a voltage signal Sr to a scan-row-fully-open pin XAO of the gate driver 12 so that the gate driver 12 simultaneously turns on the thin film transistors in all the scan rows of the pixel array 16. Thus, the charges may be rapidly discharged according to the charge neutralization, the time for completely discharging the residual charges can be shortened, and the phenomenon of the shutdown residual image can be thus eliminated.
In the LCD 10 mentioned hereinabove, the reset circuit 14 has to be added to the LCD 10 and the scan-row-fully-open pin XAO has to be added to the gate driver 12 in order to decrease the influence of the residual image and to inform the gate driver 12 to turn on the thin film transistors in all the scan rows of the pixel array 16 when the LCD 10 is shut down. In the actual circuit implementation, however, adding the reset circuit 14 and the scan-row-fully-open pin XAO increases the number of the circuit components, the area of the printed circuit board and the package area, and thus the cost greatly increases.